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السلام عليكم
عندي سؤال اخواني
ربما الكثير يعلم بان تقنية الناو في تقدم هائل
فشركة انتل في صدد انتاج رقائق سيليكون بتقنية 22 نانو
ولكن حسب علمي فجزيئات السيليكون تترتب في مجال 10 نانومتر
فهل هذه المعلومة التي اعرفها صحيحة؟؟!!
اذا نعم فهذا يعني بانه عن قريب ستتوقف الشركات عن القدرة على التطوير في السيليكون لسبب واضح و هو وصولهم للحدود الجزيئية للمادة
اريد ان تصححوا لي معلموماتي او ان تشاركو بارائكم
تقبلوا تحياتي
سلام عليكم
وعليكم السلام وأهلا بك في منتدى النانوتكنولوجي
سؤالك منطقي ماشاء الله وتفكير بالمتوقع في المستقبل
ولكن تقنية النانو كثيراً ما تفاجئنا بالنتائج المدهشة والاختراعات الغير متوقعة
لذلك لا نستبعد أن يتوصلوا بالأبحاث العلمية إلى طرق لاستمرار تطوير شرائح السليكون
وهذه مواضيع قد تفيد في هذا المجال:
Formation of Straight 10 nm Diameter Silicon Nanopores in Gold Decorated Silicon
http://pubs.acs.org/doi/abs/10.1021/nn900817d
We observe pore formation with diameters in the 10 nm range in silicon when it is covered with gold particles. This pore etching occurs when the sample is put in 5 wt % hydrofluoric acid (HF) solution for a few minutes. The pores form along the 100 direction, which is also the preferred direction of macro- and mesopores electrochemically etched into silicon. No etching occurs if the dissolved oxygen is removed from the aqueous HF solution or the gold is removed from the silicon surface. This leads to the assumption that the dissolved oxygen acts as an oxidant as in the case of stain etching with gold as cathodic material. A tentative model is suggested to explain why all of the observed nanopores have roughly the same diameter of about 10 nm. These pores can occur for inhomogeneously gold-covered planar silicon surfaces but also in MBE (molecular beam epitaxy) grown silicon nanowires since these nanowires are covered unintentionally with gold nanoclusters at their cylindrical surface.
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Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography
http://www.faqs.org/abstracts/Chemic...thography.html
Article Abstract:
A photolithography-based method capable of size reduction to produce sub-10-nm silicon nanowire arrays on a wafer scale is described. It is proposed that the application of size reduction nano-patterning method can range from the fabrication of biosensors to model catalyst systems.
author: Yang-Kyu Choi, Ji Zhu, Grunes, Jeff, Bokor, Jeffrey, Somorjai, Gabor.
Read more: http://www.faqs.org/abstracts/Chemic...#ixzz0f5kMVpDx
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Silicon Device Scaling to the Sub-10-nm Regime
http://www.sciencemag.org/cgi/conten...5704/2057?etoc
Meikei Ieong,1* Bruce Doris,2 Jakub Kedzierski,1 Ken Rim,1 Min Yang1
In the next decade, advances in complementary ****l-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.
1 IBM Semiconductor Research and Development Center, T. J. Watson Research Center, Yorktown Heights, NY 10598, USA.
2 IBM Semiconductor Research and Development Center, Microelectronic Division, Hopewell Junction, NY 12533, USA.
To whom correspondence should be addressed. E-mail: [email protected]
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Sub-10 nm silicon ridge nanofabrication by advanced edge lithography for NIL applications
http://www.sciencedirect.com/science...2d9b52ad5fdd6d
Abstract
A new nanofabrication scheme is presented to form stamps useful in thermal nanoimprint lithography (T-NIL). The stamp is created in <1 1 0> single crystalline silicon using a full-wet etching procedure including local oxidation of silicon (LOCOS) and employing an adapted edge lithography technique on top of conventional photolithography. Ridges down to 10 nm in width have been produced. The silicon ridges have no inbuilt stress and are therefore less fragile than previously fabricated oxide ridges. The ridge sample is used as a template in T-NIL and a full 100 mm wafer size imprint has been successfully carried out in both polymethylmethacrylate (PMMA) and mr-I 7020E polymer. Moreover, the imprinted pattern in PMMA is subsequently transferred into a device wafer.
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